The present invention relates to semiconductor design technology, and more particularly to a voltage generating unit for generating a high voltage supplied to a semiconductor memory device.
Semiconductor memory devices are used in various fields and one of them is used to store various data. Such semiconductor memory devices require a large capacity, a high speed, a small size, and low power consumption because they are used in desktop computers, notebook computers, and a variety of portable devices.
A technique for minimizing current consumption in a core area of a memory is being proposed as a method for designing a semiconductor memory device with low power consumption. The core area includes memory cells, bit lines, and word lines and is designed according to an ultra-fine design rule. Thus, a power supply voltage is basically lowered in order to design a semiconductor memory device, which is ultra-fine and performs high frequency operation, and a power supply voltage of 1.5 V or below is used at present.
Since a semiconductor memory device requires a low external power supply voltage and high-speed operation, it secures a low voltage margin by boosting a word line (WL) voltage and improves a sensing speed of data from a memory cell. In general, for a cell including one transistor and one capacitor, a cell transistor is configured using an NMOS transistor that occupies a smaller area than a PMOS transistor. The NMOS transistor rapidly transfers logically low data, but transfers logically high data after detecting a drop of a threshold voltage. Thus, a high voltage VPP, which is a voltage higher than an external power supply voltage VDD by a threshold voltage of a cell transistor, is used in order to read/write a complete external power supply voltage VDD from/in a cell without a loss corresponding to a threshold voltage. A boosted external power supply voltage VDD is used in a semiconductor memory device because the high voltage VPP must be higher than the external power supply voltage VDD.
FIG. 1 is a block diagram of a conventional high voltage generator circuit of a semiconductor memory device.
Referring to FIG. 1, a conventional high voltage generator circuit of a semiconductor memory device includes a reference voltage generator 10, a detector circuit 11, an oscillator circuit 12, a control circuit 13, first, second and third pump circuits 14, 15 and 16, and a cell transistor 17. The reference voltage generator 10 generates a stable reference voltage VREF. The detector circuit 11 compares the reference voltage VREF with a fed-back high voltage VPP to detect a voltage level so that the high voltage VPP can maintain a constant voltage level. On the basis of an output signal VPPE of the detector circuit 11, the oscillator circuit 12 generates a clock signal OSC for generation of the high voltage VPP. In response to the clock signal OSC of the oscillator circuit 12, the control circuit 13 controls the first, second and third pump circuits 14, 15 and 16 that generate the high voltage VPP. The cell transistor 17 receives the high voltage VPP generated by the first, second and third pump circuits 14, 15 and 16.
The conventional high voltage generator circuit compares the fed-back high voltage VPP with the reference voltage VREF generated by the reference voltage generator 10, and outputs a voltage level detection signal VPPE from the detector circuit 11 if the fed-back high voltage VPP is lower than the reference voltage VREF. The voltage level detection signal VPPE drives the oscillator circuit 12, the clock signal OSC generated by the oscillator circuit 12 is converted by the control circuit 13 into square-wave signals P1 and P2 for control of the first, second and third pump circuits 14, 15 and 16, and the square-wave signals P1 and P2 is provided to the first, second and third pump circuits 14, 15 and 16.
When the fed-back high voltage VPP is lower than the reference voltage VREF, the first, second and third pump circuits 14, 15 and 16 receive the output signals P1 and P2 of the control circuit 13, generate the high voltage VPP, i.e., a boosted external power supply voltage VDD, and provide the generated high voltage VPP to the cell transistor 17. At this point, the first, second and third pump circuits 14, 15 and 16 are identical in circuit configuration, and simultaneously receive the output signal P1 and P2 from the control circuit 13 to generate the high voltage VPP, i.e., the boosted external power supply voltage VDD. Thus, the first, second and third pump circuits 14, 15 and 16 are operated in the same time period to generate the high voltage VPP.
However, the conventional high voltage generator circuit has the following limitations.
As described with reference to FIG. 1, the conventional high voltage generator circuit generates the high voltage VPP by operating the first, second and third pump circuits 14, 15 and 16 in the same time period on the basis of the clock signal OSC of the oscillator circuit 12, which is generated repeatedly in a predetermined cycle, while the fed-back high voltage VPP is lower than the reference voltage VREF. Due to such operation, the first, second and third pump circuits 14, 15 and 16 are operated in the same time period in response to the same signal, and thus the detected peak current value is equal to the sum of the use currents of the first, second and third pump circuits 14, 15 and 16, as illustrated in FIG. 2. Thus, the conventional high voltage generator circuit causes the peak current value to be very high.
As a result, the conventional high voltage generator circuit simultaneously drives the first, second and third pump circuits 14, 15 and 16 and thus increases the swing range of a VDD current used when the high voltage VPP is generated, thus increasing the current consumption, as illustrated in FIG. 2. When a peak current value becomes higher, an excessive voltage is generated according to the peak current value, thus increasing the power consumption.